Recently, among data transmission methods, a differential transmission method is mainstream, according to which signals in opposite phases opposite to each other are sent by using two signal lines with respect to certain data, and transmission and reception are performed so as to take a differential between amplitudes of a pair of voltages of the lines as data. For example, as depicted in FIG. 10, a transmission system including the differential transmission technology is configured to be used mainly for transmission between LSI (Large Scale Integrated-circuit) chips, for example, transmission between a CPU (Central Processing Unit) and a North Bridge, and transmission between a North Bridge and a crossbar switch.
According to such differential transmission method, as depicted in FIG. 11, a data transmitting unit includes a data driver that transmits a differential signal and outputs data, and a data receiving unit includes a data receiver that receives a differential signal and takes out data. Moreover, the data receiving unit includes a phase adjusting circuit for adjusting a received clock phase to a position appropriate to data.
A general view of a conventional transmission system is depicted in FIG. 11. As depicted in the figure, according to the conventional method, transmission data and a clock synchronized with the data are output as voltage signals from a data driver and a clock driver of the data transmitting unit, and detected by a data driver and a clock receiver of the data receiving unit. When the clock receiver receives the clock, the clock receiver adjusts the clock phase to a phase that is determined by a re-training operation described later, and inputs it into the data receiver as a reception clock. The data receiver captures a voltage value with an input clock cycle as 0/1 data, and outputs it into the inside of the circuit.
Moreover, the data transmitting unit and the data receiving unit perform with a certain frequency a re-training operation of adjusting the phase by using a known data pattern so as to bring the edge position of the clock received by the data receiving unit to an appropriate position that is appropriate to reception data so that, for example, requirements of setup time and hold time are satisfied. FIGS. 12 and 13 depict a flowchart and a timing chart of a re-training operation. The re-training is controlled by respective re-training control units of the data transmitting unit and the data receiving unit.
Each of the re-training units measures time with a timer during usual operation, and asserts a re-training instruction signal after the elapse of a certain time. Here, the timers are synchronized between the data transmitting unit and the data receiving unit, and the data transmitting unit and the data receiving unit shift to the re-training operation with the same timing. During the re-training, data reception is tried by changing the clock with the phase adjusting circuit of the data receiving unit, and the clock phase is fixed to a position at which a data pattern can be correctly received.
A state of data reception by the data receiver is depicted in FIG. 14. Reception data appears as a voltage variation that continuously rises and falls, as depicted as a wave form in the upper part of the figure. With respect to the voltage variation, data is captured at a point at which the reception clock depicted in the lower part in the figure changes from 0 to 1, and data is defined to “0” or “1”.
At that time, a reference value for determining 0/1 of the data is determined in accordance with a receiving threshold voltage (Vref) of the data receiver. If the phase of the reception clock is appropriately adjusted to the variation in the received voltage, data capturing is performed in a range in which the received voltage is beyond a receiving threshold and sufficiently stable, so that correct data is output.
A state in a case where a data receiver fails in data reception is depicted in FIG. 15. When a data capturing point is close to the vicinity of a point at which the voltage variation passes through the receiving threshold, the data receiver fails in data reception, and output an incorrect value.
There is a problem that the conventional transmission method has no means of detecting phase relation between a clock and data, and cannot confirm whether data is correctly received. Moreover, there is another problem that when a phase adjustment of a receiving clock is failed, and a data capturing position is inappropriately close to a data edge, such situation cannot be detected.
Patent Document 1: Japanese Laid-open Patent Publication No. 2006-050102
Patent Document 2: International Publication Pamphlet No. WO 2004/088913